os_dev_specs (Public)
source: hikalium/os_dev_specs
[acpi_6_4]
Advanced Configuration and Power Interface (ACPI) Specification
(pdf)
- p.162: `5.2.3.2 Generic Address Structure`
- p.166: `System Description Table Header`
- p.167: `DESCRIPTION HEADER SIGNATURES`
- p.402: `6.2.10 _MAT (Multiple APIC Table Entry)`
[armv8a_pg_1_0]
ARM Cortex-A Series Version: 1.0 Programmer’s Guide for ARMv8-A
(pdf)
- p.88: 6.5.4 Hint instructions (WFI)
[cdc_1_2]
Universal Serial Bus Class Definitions for Communications Devices
(zip @ CDC1.2_WMC1.1_012011/CDC1.2_WMC1.1/usbcdc12/CDC120-20101103-track.pdf)
- p.16: 3.4.2 Data Class Interface
- p.20: 02h: Communications Device Class Code
- p.20: 02h: Communications Interface Class Code
- p.20: 06h: Ethernet Networking Control Model: Interface Subclass Code
- p.21: 0Ah: Data Interface Class
- p.25: Table 12: Type Values for the bDescriptorType Field
[ecm_1_2]
Universal Serial Bus Communications Class Subclass Specification for Ethernet Control Model Devices Revision 1.2
(zip @ CDC1.2_WMC1.1_012011/CDC1.2_WMC1.1/usbcdc12/CDC120-20101103-track.pdf)
[elf64_1_5_2]
ELF-64 Object File Format
(pdf)
[elf_1_2]
Executable and Linking Format (ELF) Specification
(pdf)
- p.78: `Dynamic Section`
- p.98: `Global Offset Table`
[hid_1_11]
Device Class Definition for HID 1.11
(pdf)
- p.17: `4.1 The HID Class (interface_class == 3 -> HID)`
- p.18: `4.2 Subclass (interface_subclass == 1 -> Boot Interface)`
- p.19: `4.3 Protocols (interface_protocol 1 -> keyboard, 2 -> mouse)`
[hpet_1_0a]
IA-PC HPET (High Precision Event Timers) Specification 1.0a
(pdf)
- p.21: `2.3.9.2.2 Periodic Mode`
- p.30: `3.2.4 The ACPI 2.0 HPET Description Table (HPET)`
[hut1_12v2]
Universal Serial Bus HID Usage Tables
(pdf)
[ich9]
Intel I/O Controller Hub 9 (ICH9) Family
(pdf)
- p.474: APIC Registers
- p.477: Redirection Table
[pci_22]
PCI Local Bus Specification
(pdf)
- p.211: Capabilities Pointer
- p.211: Figure 6-1: Type 00h Configuration Space Header
- p.222: BAR: Base Address Register
- p.233: 6.7 Capabilities List
[pcie_20]
PCI Express Base Specification
(pdf)
- p.415: Figure 7-3: PCI Express Configuration Space Layout
- p.416: 7.2.2. PCI Express Enhanced Configuration Access Mechanism (ECAM)
- p.426: 7.5.1. Type 0/1 Common Configuration Space
[rtl8139d]
RTL8139D DataSheet
(pdf)
- p.10: Register Descriptions
- p.12: 5.1 Receive Status Register in Rx packet header
[rtl8139pg]
RTL8139 Programming guide
(pdf)
- p.2: Transmission process
- p.6: Receive process
[sdm_vol1]
Intel SDM Vol.1
(pdf)
- p.161: 6.5.1 Call and Return Operation for Interrupt or Exception Handling Procedures
- p.167: 6.5.6 Interrupt and Exception Behavior in 64-Bit Mode
[sdm_vol2]
Intel SDM Vol.2
(pdf)
- p.319: CPUID list
- p.331: EAX=0x15 Time stamp counter and nominal core crystal clock info leaf
- p.1403: SYSCALL
- p.2215: APPENDIX B INSTRUCTION FORMATS AND ENCODINGS
[sdm_vol3]
Intel SDM Vol.3
(pdf)
- p.67: 2.2 MODES OF OPERATION
- p.69: 2.2.1 Extended Feature Enable Register
- p.70: 2.3 SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER
- p.134: Figure 4-11. Formats of CR3 and Paging-Structure Entries with 4-Level Paging and 5-Level Paging
- p.139: 4.7 PAGE-FAULT EXCEPTIONS
- p.180: 5.8.8 Fast System Calls in 64-Bit Mode
- p.181: Figure 5-14. MSRs Used by SYSCALL and SYSRET
- p.194: 6.3 SOURCES OF INTERRUPTS
- p.269: 7.7 TASK MANAGEMENT IN 64-BIT MODE
- p.384: Table 10-1. Local APIC Register Address Map
- p.387: `IA32_APIC_BASE MSR`
- p.390: LVT Timer Register (FEE0 0320H)
- p.391: Figure 10-8. Local Vector Table (LVT)
- p.395: 10.5.4 APIC Timer
- p.416: 10.12.1 Detecting and Enabling x2APIC Mode
- p.436: 11.3 METHODS OF CACHING AVAILABLE
- p.442: Table 11-5. Cache Operating Modes
- p.465: Table 11-11. Selection of PAT Entries with PAT, PCD, and PWT Flags
- p.660: 17.17.1 Invariant TSC
- p.832: 19.7 COUNTING CLOCKS ( Bus Clock, Core Crystal Clock, Time-stamp counter )
- p.834: 19.7.3 Determining the Processor Base Frequency
[sdm_vol4]
Intel SDM Vol.4
(pdf)
- p.20: `IA32_APIC_BASE`
- p.20: `IA32_TIME_STAMP_COUNTER`
- p.22: `IA32_TSC_ADJUST`
- p.81: `MSR_FSB_FREQ` (Bus Clock)
[sysv_abi_0_99]
System V Application Binary Interface - AMD64 Architecture Processor Supplement
(pdf)
- p.22: `Figure 3.4: Register Usage`
- p.124: `A.2 AMD64 Linux Kernel Conventions`
[uefi_2_9]
Unified Extensible Firmware Interface (UEFI) Specification
(pdf)
- p.169: `EFI_SYSTEM_TABLE`
- p.177: `EFI_CONFIGURATION_TABLE`
- p.586: `EFI_SIMPLE_FILE SYSTEM_PROTOCOL.OpenVolume()`
- p.588: `typedef struct _EFI_FILE_PROTOCOL`
- p.589: `EFI_FILE_PROTOCOL.Open()`
- p.605: `EFI_FILE_INFO`
[usb_2_0]
Universal Serial Bus Specification Revision 2.0
(zip @ usb_20_20190524/usb_20.pdf)
- p.268: Figure 9-1. Device State Diagram
- p.276: bmRequestType bitmap
- p.278: 9.4 Standard Device Requests
- p.279: Table 9-4. Standard Request Codes
- p.279: Table 9-5. Descriptor Types
- p.281: 9.4.3 Get Descriptor Request
- p.282: All devices must provide a device descriptor and at least one configuration descriptor
- p.297: 9.6.6 Endpoint Descriptor
- p.301: 9.6.7 String Descriptor
[usb_type_c]
Universal Serial Bus Type-C Cable and Connector Specification
(pdf)
[xhci_1_2]
eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Requirements Specification May 2019 Revision 1.2
(pdf)
- p.64: Figure 3-4: Transfer ring
- p.66: Figure 3-6: Simple Transfer Example
- p.69: Figure 3-8: Control Transfer Descriptor Example
- p.83: 4.3 USB Device Initialization
- p.91: 4.3.6 Setting Alternate Interfaces
- p.107: No Op command
- p.161: 4.8.2 Endpoint Context Initialization
- p.163: Figure 4-5: Endpoint State Diagram
- p.300: Figure 4-25: USB2 Root Hub Port State Machine
- p.370: Register Attributes
- p.406: 5.4.8 Port Status and Control Register (PORTSC)
- p.439: Data structure requirements
- p.454: 6.2.3.2 Configure Endpoint Command Usage
- p.456: 6.2.3.6 Interval
- p.459: 6.2.5 Input Context
- p.461: 6.2.5.1 Input Control Context
- p.491: 6.4.3.5 Configure Endpoint Command TRB
- p.507: TRB Completion Codes
- p.511: Table 6-91: TRB Type Definitions